Senior/Staff Process Engineer (Wafer Dicing & Back-grind)

Core Responsibilities

• Responsible for silicon photonic wafer backside grinding/thinning process, laser stealth dicing process and die sorting development for silicon photonic chips, with OSAT or internal line.

• Optimize wafer thinning thickness, grinding speed, cutting path and laser cutting parameters to avoid chip crack, edge chipping and optical structure damage of silicon photonic wafers.

• Solve process abnormalities in wafer thinning and dicing processes, including wafer warpage, surface scratch, incomplete cutting and chip breakage.

• Monitor wafer thickness uniformity, cutting quality and production capacity, carry out continuous process optimization to improve product yield.

• Evaluate process compatibility between wafer grinding/stealth dicing and bumping & flip-chip processes, optimize process integration to avoid subsequent process failure attributed to front-end process variations.

• Compile process SOP, WI, failure reports and engineering change documents; support NPI new product introduction and process verification.

Key Requirements & Qualification

• Education: A Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline.

• Experience: 3 to 6+ years of hands-on process engineering in wafer mounting, stealth dicing, wafer grinding, especially in handling advanced packaging wafers with more complex topology or stack.

• Experience working with external equipment and material suppliers to develop equipment and materials needed to support new assembly requirements. Characterize, qualify and bring the process up for mass production.

• Familiarity with SPC, JMP data analysis, and DOE matrix design for process development and problem identification and solving using meticulous fixing methods.

This process engineering role develops and improves wafer grinding, thinning, laser dicing, and die-sorting processes for silicon photonic chips. The work spans process troubleshooting, yield and quality improvement, process integration, and preparation for new-product and mass-production readiness.

Role at a glance

Skills mentioned

What you will likely work on

• Develop wafer backside grinding, thinning, stealth dicing, and die-sorting processes for silicon photonic chips.
• Tune wafer thickness, grinding speed, cutting paths, and laser parameters to reduce damage and defects.
• Investigate process issues such as warpage, surface scratches, incomplete cuts, and die breakage.
• Track thickness uniformity, cut quality, and production capacity, then improve process yield.
• Check compatibility with bumping and flip-chip steps and reduce downstream failures from upstream variation.
• Work with equipment and material suppliers to develop, characterize, and qualify processes for new assembly needs and mass production.
• Prepare process instructions, work instructions, failure reports, and engineering change documents; support NPI and process verification.

Good fit signals

• Has 3 to 6+ years of hands-on process engineering experience in wafer mounting, stealth dicing, or wafer grinding.
• Has worked with advanced packaging wafers with complex topology or stacks.
• Can develop and troubleshoot wafer processes using SPC, JMP analysis, and DOE matrix design.
• Has experience coordinating with external equipment and material suppliers and qualifying processes for production.
• Holds a bachelor's or master's degree in a relevant engineering or materials discipline, or an equivalent technical qualification.