Senior/Staff Process Engineer (Flip Chip)

Core Responsibilities

1. Owns the process development and technical support of the Flip Chip process for silicon photonic chip wafers, with OSAT or internal line. Process may include plasma cleaning, flux engineering, pick & place, reflow, underfill, curing and/or TCB/NCP flux-less flow.

2. DOE to characterize process window and margin. Optimize process integration with upstream processes (e.g. bump/FO) to increase yield and manufacturability.

3. Material Characterization & Selection: Evaluate and qualify new manufacturing raw materials, including NCP, flux, underfill etc, as applicable.

4. Design and execute DOE plans to characterize thermal and mechanical stress. Lead reliability validations including Temperature Cycling Test (TCT), Unbiased Highly Accelerated Stress Test (HAST) and High-Temperature Storage (HTS).

5. Failure Analysis & Debug: Own the root-cause diagnostics of structural failure modes unique to FC (e.g. flux void, residue, misalignment, die warpage, reflow anomaly, underfill void etc), and formulate improvement solutions.

6. Manage incoming material quality control, establish SPC control plans and monitor process variation to ensure long-term process stability.

7. Compile process SOP, WI, process failure reports and engineering change documents; support NPI new product introduction and process verification.

Key Requirements & Qualifications

• Education: Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline.

• Experience: 5+ years of hands-on industry experience in flip chip assembly.

• Technical Knowledge:

• Deep practical understanding of plasma cleaning, flux engineering, pick & place, reflow, underfill, curing and/or TCB/NCP flux-less flow.

• Comprehensive command of finite element simulation principles regarding warpage, thermal dissipation, and structural mechanical integrity.

• Solid working expertise with industry validation methodologies including FMEA, SPC controls, and structured 8D problem-solving tools.

• Software Tools: High proficiency with robust analytical platforms like JMP, Minitab.

Develop and support flip-chip assembly processes for silicon photonic wafers, from process-window optimization through reliability validation and failure analysis. The role also covers material qualification, process controls, documentation, and support for new product introduction.

Role at a glance

Skills mentioned

What you will likely work on

• Develop and provide technical support for flip-chip wafer assembly processes, including applicable cleaning, placement, bonding, reflow, and underfill steps.
• Use DOE to define process windows and margins, and improve integration with upstream processes to support yield and manufacturability.
• Assess and qualify manufacturing materials such as flux, underfill, and NCP.
• Plan and run thermal and mechanical stress studies, and lead reliability validation using TCT, HAST, and HTS methods.
• Diagnose flip-chip defects, identify root causes, and develop corrective process improvements.
• Set incoming-material quality checks and SPC controls, then monitor process variation and stability.
• Prepare process SOPs, work instructions, failure reports, and engineering change documentation; support NPI and process verification.

Good fit signals

• You bring at least five years of hands-on industry experience in flip-chip assembly.
• You have practical knowledge across relevant flip-chip process steps, including flux, placement, reflow, and underfill.
• You can apply finite element simulation principles to warpage, heat transfer, and structural integrity questions.
• You have working expertise in FMEA, SPC, and structured 8D problem solving.
• You are proficient with JMP or Minitab for engineering analysis.