IC/RTL Design Engineer

IC/RTL Design Engineer/ Front-End Engineer

About the role. You design and implement the digital front-end RTL at the heart of the chip — including the high-speed datapath that moves data between UCIe and the optical front end. Guided by the interface specs and coding standards, you take blocks from micro-architecture through clean, timing-aware RTL and block-level verification. It's a hands-on role with room to grow your scope as the team and the chip mature.

What you'll do

• Develop block-level micro-architecture for your assigned blocks, and contribute to interface and register definitions.

• Design and implement front-end RTL blocks in SystemVerilog — datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.

• Integrate IP and support parameterization for configurability.

• Write clean, lint-clean, CDC/RDC-clean RTL that follows the coding and quality standards.

• Write block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before handoff to DV.

• Power- and timing-aware design — managing block activity, clock-gating, pipelining, and retiming; partner with the backend team on physical closure for your blocks.

• Bring-up and debug across simulation and emulation / FPGA prototyping; support DV and silicon bring-up, including DFT/debug hooks in your blocks.

• Collaborate with the architecture, modelling, DV, DFT, and backend teams as your blocks move through the flow.

Required

• BS or MS in Electrical/Computer Engineering (or equivalent experience).

• 3+ years of digital RTL design in SystemVerilog, with blocks taken from micro-architecture through to verification handoff.

• Solid digital design fundamentals: pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI).

• Lint and CDC/RDC discipline and clean-RTL practices.

• Power- and timing-aware design practices; comfort with synthesis and timing closure, working with the backend team.

• Strong debug skills in simulation; scripting in Python, Perl, or TCL.

Preferred

• High-speed datapath, SerDes-adjacent, or interface design exposure (UCIe, PCIe/CXL, or similar).

• FEC/coding datapath familiarity (e.g., Reed-Solomon) and gray-code mapping.

• Assertion-based verification (SVA) and familiarity with UVM block-level testbenches; emulation / FPGA prototyping experience.

• Exposure to scale-up / scale-out interconnects or network switch / NIC / memory-controller datapaths.

• Low-power / UPF and DFT (scan) concepts.

• Optical transceiver, CPO, or linear-drive optics background; advanced-node (N5/N3/N2) design experience.

This hands-on IC/RTL Design Engineer role develops digital front-end logic for a chip, from block micro-architecture through timing-aware RTL and verification handoff. The work centers on datapath and interface blocks, including a UCIe adapter, with collaboration across design, verification, and backend teams.

Role at a glance

Skills mentioned

What you will likely work on

• Define block micro-architecture and contribute to interface and register specifications.
• Implement SystemVerilog datapath, UCIe streaming/RDI adapter, FIFO, and supporting logic; integrate and parameterize IP.
• Produce lint-clean and CDC/RDC-clean RTL that follows design and quality standards.
• Build block-level testbenches, sanity checks, and assertions before verification handoff.
• Apply power and timing techniques such as activity management, clock gating, pipelining, and retiming; work with backend engineers on physical closure.
• Debug through simulation and emulation or FPGA prototyping, and support design verification and silicon bring-up, including DFT/debug hooks.
• Coordinate block progress with architecture, modeling, verification, DFT, and backend teams.

Good fit signals

• You have at least three years of digital RTL design experience using SystemVerilog, including blocks carried from micro-architecture to verification handoff.
• You bring solid digital design knowledge spanning pipelining, FSMs, FIFOs, CDC, and streaming or bus interfaces.
• You are comfortable with lint and CDC/RDC practices, synthesis, timing closure, and simulation debugging.
• You can script in Python, Perl, or TCL; experience with high-speed interfaces, verification methods, or optical/interconnect datapaths is an advantage.